1. Field of the Invention
The present invention relates to pulse width modulation (PWM) signal generators. In particular, the invention relates to PWM signal generators with a programmable period and duty cycle.
2. Description of the Related Art
Pulse width modulation (PWM) signal generator circuits are used in many kinds of circuits, including embedded controllers and motor control circuits.
FIG. 1 is a block diagram of an existing PWM timing circuit 30, including a period shadow register 32, a period register 34, a period comparison circuit 36, a counter 38, a duty cycle comparison circuit 40, a duty cycle register 42, a duty cycle shadow register 44, and a set-reset latch 46.
Period register 34 stores a period value and duty cycle register 42 stores a duty cycle value. Counter 38 increments a count value on pulses of a clock signal 48. When the count value equals the duty cycle value (called a xe2x80x9cduty cycle matchxe2x80x9d), duty cycle comparison circuit 40 generates a duty cycle match signal 50, causing set-reset latch 46 to reset an output signal 52. Then, when the count value equals the period value (called a xe2x80x9cperiod matchxe2x80x9d), period comparison circuit 36 generates a period match signal 54, causing set-reset latch 46 to set the output signal 52 back to its original state. Also at that time, the count value is reset, an updated period value is loaded from the period shadow register 32 into the period register 34, and an updated duty cycle value is loaded from the duty cycle shadow register 44 into the duty cycle register 42.
A computer program generates the updated period value and updated duty cycle value, and also generates a write data signal to indicate to the shadow registers 32 and 44 that they should load the updated values.
In this manner, the output signal 52 is a pulse width modulated signal with a programmable period as determined by the updated period value and a programmable duty cycle as determined by the updated duty cycle value.
FIG. 2 illustrates a potential problem with PWM timing circuit 30 using a specific example. Line 62 corresponds to the count value. Initially, the period value is ten and the duty cycle value is three, so the output signal 52 corresponds to these values. At time 64, the updated period value of eight is written into period shadow register 32. At time 66, the count value matches the period value, so the period value is replaced by the updated period value in period register 34 and the count value is reset. At time 68, the updated duty cycle value of two is written into duty cycle shadow register 44. However, the output signal 52 uses the current duty cycle value of three, instead of the updated duty cycle value of two, until time 70 (the next period match).
Thus, a predictable output signal does not result when the period and duty cycle are updated, unless both can be updated before the period match.
A related concern is that the minimum period value is determined by the maximum time the software requires to update the period and duty cycle shadow registers 32 and 44.
A potential solution is for the software to monitor the count value and to allow updates of the period value and duty cycle value to occur only when both can be accomplished before the period match. Some existing programs include a polling loop or an interrupt to monitor the count value. However, these extra software features increase the load on the processor that runs the software. These concerns are increased when the software controls more than one embedded system, each having its own count value that requires monitoring. Thus, there is a need for a solution that reduces the processor load.
The present invention addresses these and other problems of existing PWM signal generator circuits by providing an update sequencer circuit.
According to one embodiment, an apparatus according to the present invention includes a pulse width modulation (PWM) timing circuit for generating a signal having a programmable period and a programmable duty cycle. The apparatus includes a storage element, a counter, a comparison circuit, and an update sequencer circuit. The storage element is configured to store at least a period value and a duty cycle value. The counter is configured to receive a clock signal and in accordance therewith generate a count value. The comparison circuit is coupled to the storage element and the counter. The comparison circuit is configured to compare the count value, the period value, and the duty cycle value, and in accordance therewith generate a period match signal and an output signal. The update sequencer circuit is coupled to the storage element and the comparison circuit. The update sequencer circuit is configured to detect an updated period value and an updated duty cycle value, and to receive the period match signal, and in accordance therewith selectively generate a period write signal and a duty cycle write signal. The storage element is further configured to receive the updated period value, the updated duty cycle value, the period write signal, and the duty cycle write signal, and in accordance therewith replace the period value with the updated period value and the duty cycle value with the updated duty cycle value.
According to another embodiment, a method according to the present invention generates a signal having a programmable period and a programmable duty cycle. The method includes the steps of storing at least a period value and a duty cycle value; receiving a clock signal; generating a count value in response to said clock signal; comparing the count value, the period value, and the duty cycle value, and in accordance therewith generating a period match signal and an output signal; detecting an updated period value and an updated duty cycle value; generating a period write signal and a duty cycle write signal in accordance with the updated period and duty cycle values; and replacing the period value with the updated period value and the duty cycle value with the updated duty cycle value.